Performance Analysis of Modified Qserl Circuit

This work is based on a new approach for minimizing energy consumption in quasi static energy recovery logic (QSERL) circuit which involves optimization by removing the non adiabatic losses completely. Energy recovering circuitry based on adiabatic principles is a promising technique leading towards lowpower high performance circuit design. The efficiency of such circuits may be increased by reducing the adiabatic and non-adiabatic losses drawn by them during the charging and recovery operations. In this paper, performance of the proposed logic style is analyzed and compared with CMOS in their representative inverters, gates, flip flops and adder circuits. All the circuits were simulated by VIRTUOSO SPECTRE simulator of Cadence in 0.18μm technology. In our proposed inverter the energy efficiency has been improved to almost 30% & 20% upto 20MHz and 20fF external load capacitance in comparison to CMOS & QSERL circuits respectively. Our proposed circuit provides energy efficient performance up to 100 MHz and thus it has proven to be used in high-performance VLSI circuitry.